Digital IC Design and Signoff from Cadence

In today’s rapidly evolving landscape, designs are growing in size and complexity. As a result, achieving the desired power, performance, and area (PPA) targets has become increasingly challenging. Furthermore, tight schedules further intensify the engineering task at hand. However, Cadence® has developed an integrated digital IC design full flow that addresses these difficulties by incorporating groundbreaking innovations that transcend the limitations of individual tools. By integrating core engines and key technologies, the Cadence digital full flow empowers customers to surpass their PPA objectives ahead of schedule.

Design Creation:

  • Logic Equivalence Checking
  • Functional ECO
  • Low-Power Validation
  • Synthesis
  • Power Analysis
  • Constraints and CDC Signoff
  • Test


  • Innovus Implementation and Floorplanning
  • Integrity 3D-IC
  • Cadence Cerebrus Intelligent Chip Explorer


  • Silicon Signoff and Verification
  • Library Characterization


  • 3D-IC Design
  • Advanced Node
  • Arm®-Based Designs
  • Low Power
  • Mixed-Signal Design
  • AI / Machine Learning Solutions

Product datasheets

Virtuoso, Assura Physical Verification

A key component of the design verification suite of tools within Virtuoso® Platform

Physical Verification System

In-design and back-end physical verification, constraint validation, and reliability checking

MaskCompose Reticle and Wafer Synthesis Suite

New levels of automation and efficiency for the tapeout environment

QuickView Signoff Data Analysis Environment

Easy-to-use, high-performance, and standalone chip-finishing system

Encounter Conformal ECO Designer

Implement RTL engineering change orders (ECOs) for pre- and post-mask layout

Encounter Conformal Low Power

Verify and debug milliongate low power designs without gate-level simulations

Encounter Conformal Equivalence Checker

Verify and debug multi-million–gate designs without using test vectors

First Encounter Design Exploration and Prototyping

Comprehensive flat and hierarchical design planning, analysis, and debug environment

Genus Synthesis Solution

Massively parallel RTL synthesis and physical synthesis

Innovus Implementation System

A physical implementation tool for high-density designs

Joules RTL Power Solution

Unified power calculator for accurate RTL power and signoff-quality gate power

Modus DFT Software Solution

Physically aware design-for-test, automatic test patterns, and silicon diagnostics tool

Pegasus Verification System

Physical verification solution reducing signoff from days to hours

Quantus QRC Extraction Solution

Parasitic extraction tool for digital and custom/analog flows

Stratus High-Level Synthesis

Create RTL design implementations for ASIC, SoC and FPGA from C++/SystemC