Allegro X Advanced Package Designer (APD)

Optimized physical layout solution for single- and multi-die packages with a correct-by-construction database, real-time DRC of physical design rules and electrical constraints

Support for all chiplet attach methods

• Bond wire, flip chip, stacked, embedded, etc.

Flexible connectivity model, supporting netlist, schematic, and “on-the-fly” connectivity

Robust set of packaging-specific features

• Technology file-driven package substrate style stack-up
• On-the-fly library development
• Multi-tiered wire-bonding
• Visualize and perform 3D wire and design rule checks
• 3D stacking/multi-stack intelligence, 2-sided die support, embedded cavities, and chip/package co-design based on XDA die abstract
• Push/shove, any angle, and snake routing
• Reports and manufacturing outputs

Includes core DesignTrue™ DFM rule checking, 3D Viewer

Recommended Additional Products

• Allegro X APD Layout (Allegro X Advanced Package Designer + SiP Layout option)
• Allegro X Symphony Team Design Option
• Allegro X Productivity Toolbox
• Sigrity X Aurora IC Package Analysis
• Allegro X APD RF Layout Option
• Allegro X Integrity 3D-IC Option

For Silicon Interposers:

• Allegro X Silicon Layout Option
• Physical Verification Design Rule Checker (PVS)